1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, it relates to a semiconductor device such as a power MOSFET and IGBT (Insulated gate bipolar transistor) with increased breakdown voltage and a method of fabricating the same.
2. Description of the Background Art
FIG. 1 is a sectional view showing a plurality of basic MOS unit cells of a conventional n channel power MOSFET device.
Referring to FIG. 1, an n.sup.- drain region 1b is superposed on the upper surface of an n.sup.+ drain region 1a. A plurality of separate p semiconductor regions 2 are selectively formed in the surface of the n.sup.- drain region 1b. N.sup.+ source regions 3 are selectively formed in the surfaces of the p semiconductor regions 2, each of which is spaced by a predetermined interval from the n.sup.- drain region 1b. Channel regions 4 are defined near portions of the surfaces of the p semiconductor regions 2 between the n.sup.+ source regions 3 and the n.sup.- drain region 1b. Gate insulation films 5 are formed on the channel regions 4, and gate electrodes 6 are superposed thereon. Further, a source electrode 7 is formed to connect and short-circuit the central portions of the surfaces of the p semiconductor regions 2 and parts of the surfaces of the n.sup.+ source regions 3. The gate electrodes 6 and the source electrode 7 are electrically isolated by layer insulation films 8 interposed therebetween. A drain electrode 9 is formed on the bottom surface of the n.sup.+ drain region 1a.
An operation of the conventional semiconductor device in FIG. 1 will now be described. A drain voltage V.sub.DS is applied across the drain electrode 9 and the source electrode 7. When a gate voltage V.sub.GS is applied across the gate electrodes 6 and the source electrode 7, inversion layers are formed in the channel regions 4. A drain current I.sub.D flows between the drain electrode 9 and the source electrode 7 through the channel regions 4. The drain current I.sub.D is controlled by the gate voltage V.sub.GS. A potential at the channel regions 4 are fixed by connecting and short-circuiting the central poritons of the surfaces of the p semiconductor regions 2 and the parts of the surfaces of the n.sup.+ source regions 3 with the source electrode 7.
The power MOSFET is liable to break down in such a manner as will be described below. FIG. 2 is a graph illustrating an output characteristic of the power MOSFET shown in FIG. 1. The axis of ordinate of the graph represents the drain current I.sub.D and the axis of abscissa represents the drain voltage V.sub.DS. A parameter is the gate voltage V.sub.GS. When the drain voltage V.sub.DS reaches the breakdown voltage V.sub.C, the drain current I.sub.D rapidly increases to cause the breakdown state of the power MOSFET device. The power MOSFET device tends to be instantaneously destroyed when the breakdown current J.sub.C becomes large to the extent of exceeding a certain critical value.
FIG. 3A is a schematic sectional view showing a power MOSFET and FIG. 3B is a similar schematic sectional view of the power MOSFET to which a diagram of its equivalent circuit is superposed. Referring to FIG. 3A, there are internal resistances R.sub.1 and R.sub.a near the respective n.sup.+ source regions 3 in the p semiconductor region 2. The internal resistance R.sub.1 extends in a direction corresponding to the depth of each n.sup.+ source region 3 while the internal resistance R.sub.a extends in a direction along the bottom surface of each n.sup.+ source region 3. In FIG. 3B, these internal resistances are replaced with a composite internal resistance R.sub.2 extending in a direction corresponding to the depth of the n.sup.+ source regions 3 and the internal resistances R.sub.a extending in a direction along the bottom surfaces of the n.sup.+ source regions 3 in the p semiconductor region 2. The internal resistances R.sub.a serve as a base resistance of a parasitic transistor T.sub.r composed of the n.sup.- drain region 1b, the p semiconductor region 2 and the n.sup.+ source regions 3. The n.sup.- drain region 1b and the p semiconductor region 2 form a diode D.
When the drain voltage V.sub.DS applied across the source electrode 7 and the drain electrode 9 is increased and reaches the breakdown voltage of the diode D defined by the n.sup.- drain region 1b and the p semiconductor region 2, the breakdown current J.sub.C beings to flow as indicated with arrows in FIG. 3A. When the breakdown current J.sub.C flows just under the bottom surfaces of the n.sup.+ source regions 3, the base potential of the parasitic transistor T.sub.r rises. The parasitic transistor T.sub.r becomes conductive when the potential difference between the base and the emitter becomes more than 0.6V. This condition is given by the following equation: EQU J.sub.C .times.R.sub.a &gt;0.6 (V) (1)
It should be noted that the composite internal resistance R.sub.2 extending in the direction corresponding to the depth of the n.sup.+ source regions 3 is sufficiently smaller than the internal resistances R.sub.a and therefore it is negligible. When the breakdown current J.sub.C which satisfies the equation (1) flows into the transistor T.sub.r, it becomes conductive.
At this time, the collector current flowing in the parasitic transistor T.sub.r is equal to the product of the base current and a direct current amplification factor h.sub.FE of the parasitic transistor T.sub.r. Usually, the value of the direct current amplification factor h.sub.FE is very large, and hence the collector current flowing in the parasitic transistor T.sub.r is also very large. Thus, when a breakdown voltage is lower in some part than in other parts, no matter how slight the difference may be, the flow of current concentrates in such area, ultimately resulting in breaking down the power MOSFET.
A conventional semiconductor device such as a power MOSFET structured as has been described has an insufficient to breakdown voltage, and therefore it tends to be instantaneously destroyed due to overload.